The vast majority of present day electronic systems use metal oxide semiconductor (MOS) integrated circuits (ICs). It is increasingly common for different types of MOS circuits to be used in a given system. For example, older MOS devices typically operate from a five volt power supply. However, newer MOS devices are now available which operate with reduced power supply voltages such as three volts, or even two volts. Reducing the power supply voltage conserves power and increases operating speed. In other situations, a reduced logic voltage level, such as two volts, may be used to transmit signals along a bus which interconnects a large number of MOS components which individually operate at the five volt level. This also provides reduced power consumption and increased operating speed for the circuits connected to the bus.
Certain circuit designs are known which provide level shifting between five volt logic signals and two volt logic signals. Unfortunately, because the MOS transistors in such circuits must necessarily be coupled to two different supply voltages, they are prone to a so-called latch-up problem. In particular, such a circuit typically contains a stage consisting of a P-channel pull-up transistor connected to a five volt supply, and an output node, with an N-channel pull-down transistor coupled to a ground reference supply and the output node. This arrangement is quite common in the standard input or output stage of a complimentary metal oxide semiconductor (CMOS) logic circuit, and also exists in a CMOS logic circuit which uses the P-channel device for electrostatic discharge protection, i.e., an open drain output.
Parasitic bipolar transistors are created between the P-type and N-type regions in such a circuit. This is not normally a problem, but can become so if the parasitic bipolar transistors are biased to an active, or on, state. This may occur if an external voltage such as terminating voltage is applied to the output pin before the supply voltage is applied. If the terminating voltage is supplied to the output pin first, the parasitic transistors may become forward biased, and draw enough current to cause the MOS devices to remain latched in a particular state, with potentially damaging results.
The latch-up problem is not particularly difficult to solve in a system having a central power supply which serves all of the integrated circuits interconnected by the bus. In such a system, the central power supply may include a delay circuit which prevents the terminator volt power supply from operating until after the supply voltage is available.
However, in certain other system configurations the power supply-induced latch-up problem is more difficult to handle. For example, the system designer may require that each circuit board module have its own power supply that operates independently of the power supplies on the other modules. This has an advantage in that the total power dissipation automatically scales as modules are inserted or removed, which is particularly advantageous in a system such as a digital computer, where various system configurations require various different types and numbers of modules.
However, the bus interface latch-up problem can be difficult to solve in a distributed power supply system. Even if each power supply contains a delay circuit, a termination supply signal originating on a particular module which is operating properly may be passed along the bus to a module which has a malfunctioning power supply. As a result, the devices connected to the bus in the malfunctioning module may still enter latch-up. A latch-up problem can also occur when one of the power supplies fails during normal operation, or during a power-down sequence, when the power supplies on different modules are disabled at different times.
What is needed is a way to prevent power supply-induced latch-up in MOS integrated circuits that operate off of two or more different supply voltages, where the system uses multiple distributed power supplies that are physically located on a number of different circuit board modules.